1. Field of the Invention
The present invention relates to a protection circuit, and more particularly, to an electrostatic discharge (ESD) protection circuit.
2. Description of the Related Art
Due to the innovation of manufacturing technology, semiconductor circuits require lower and lower operating voltage, thus saving power. Since voltages provided to semiconductor circuits are not an ideally standard value, abnormal high-voltage electrostatic voltage noises occur from time to time. If not curbed, these high-voltage electrostatic voltage noises may easily damage semiconductor circuits during operation. Accordingly, the prevention of integrated circuits from the damage of electrostatic voltage noises is the duty of protection circuits.
FIG. 1 is a schematic block circuit diagram showing an ESD protection circuit structure. Referring to FIG. 1, the ESD protection circuit structure comprises two ESD protection clamping circuits 130 and 135, and two ESD protection circuits 140 and 145. Wherein, the circuit to be protected includes the integrated circuits 105 and 110, and the interface circuit 130 between the integrated circuits 105 and 110. These ESD protection circuits 140 and 145 are circuits having the same function.
The integrated circuit 105 is coupled to the first power source Vdd1 and the first ground terminal GND1. The integrated circuit 110 is coupled to the second power source Vdd2 and the second ground terminal GND2. The interface circuit 120 is electrically coupled to the first power source Vdd1, the first ground terminal GND1, the second power source Vdd2, and the second ground terminal GND2.
If the first power source Vdd1 has an electrostatic voltage noise, theoretically, the ESD clamping circuit 130 and the ESD protection circuit 140 are immediately turned on. The current generated from the electrostatic voltage noise then flows to the first ground terminal GND1 and the second power source Vdd2 through the ESD clamping circuit 130 and the ESD protection circuit 140 such that the noise current would not flow through and damage the integrated circuit 105 and the interface circuit 120. In contrary, if the second power source Vdd2 has an electrostatic voltage noise, the ESD clamping circuit 135 and the ESD protection circuit 145 are immediately turned on. The current generated from the electrostatic voltage noise flows to the second ground terminal GND2 and the first power source Vdd1 through the ESD clamping circuit 135 and the ESD protection circuit 145 such that the noise current would not flow through and damage the integrated circuit 110 and the interface circuit 120.
In the prior art, these ESD protection circuits 140 and 145 are usually made of diodes or silicon controlled rectifiers (SCRs), characterized by the low operating voltage and low generating power. The SCRs include lateral SCRs (LSCRs), and low-voltage trigger SCRs (LVTSCRs).
FIG. 2 is schematic block circuit and cross sectional configurations showing a conventional ESD protection circuit in FIG. 1. The conventional SCR is a LSCR. The LSCR comprises a positive-channel metal-oxide-semiconductor (PMSO) transistor and an N+-well region, which is named a P-type SCR (PSCR). In another example, the LSCR may comprise a negative-channel metal-oxide-semiconductor (NMSO) transistor and a P+-well region, which is named an N-type SCR (NSCR). In order to illustrate the operating theory, an equivalent PMOS transistor diagram is added in the left configuration of FIG. 2, and an equivalent NMOS transistor diagram is added in the right configuration of FIG. 2. These two circuits in FIG. 2 have the same function.
The circuit in the left configuration of FIG. 2 comprises two PSCRs 141a and 143a, wherein the control gate of the PMOS transistor of the PSCR 141a is coupled to the first power source Vdd1, and the control gate of the PMOS transistor of the PSCR 143a is coupled to the second power source Vdd2. Other connection specifics are shown in FIG. 2. While the first power source Vdd1 generates a higher positive electrostatic voltage noise, at this moment the voltage difference between the control gate of the PMOS transistor and the anode (the source of the PMOS transistor) of the PSCR 143a is higher than the threshold voltage of the PMOS transistor. Accordingly, a current path is generated and the first and the second power sources Vdd1 and Vdd2 are connected through the PSCR 143a. Usually, the threshold voltage is 0.4˜2V. For simple descriptions, all threshold voltages described below are 1V.
Accordingly, while the second power source Vdd2 generates a higher-voltage electrostatic voltage noise, at this moment, the voltage difference between the control gate of the PMOS transistor and the anode (the source of the PMOS transistor) of the PSCR 141a, is higher than the threshold voltage, about 1V, of the PMOS transistor. Accordingly, a current path is generated and the first and the second power sources Vdd1 and Vdd2 are connected through the PSCR 141a such that the current generated from the electrostatic voltage noise will not damage internal circuits.
The circuit in the right configuration of FIG. 2 comprises two NSCRs 141b and 143b, wherein the control gate of the NMOS transistor of the NSCR 141b is coupled to the power source Vss2, and the control gate of the NMOS transistor of the NSCR 143b is coupled to the power source Vss1. Other connection specifics in the circuit are shown in FIG. 2. The source voltages Vss1 and Vss2 are similar to the first and the second power sources Vdd1 and Vdd2. When the power source Vss1 generates a higher positive electrostatic voltage noise, at this moment, the voltage difference between the control gate of the NMOS transistor and the cathode (the source of the NMOS transistor) of the NSCR 141b is higher than the threshold voltage, about 1V, of the NMOS transistor. Accordingly, a current path is generated and the power sources Vss1 and Vss2 are connected through the NSCR 143b such that the current generated from the electrostatic voltage noise will not damage internal circuits. The operating theory of the NSCR 141b is similar to that of the NSCR 143b. Detailed descriptions are not repeated.
In the conventional ESD protection circuit of the ESD protection circuit structure, when the voltage difference between the first power source Vdd1 and the second power source Vdd2 is larger than 1V, the ESD protection circuit is tuned on so these integrated circuits 105 and 110 cannot receive correct data from external circuits. Therefore, only when the voltage difference between the first and the second power sources is lower than 1V may the conventional ESD protection circuit be used, or only when multiple ESD protection circuits are connected in series so that the voltage difference between the first and the second power sources is higher than 1V may the conventional ESD protection circuit be used. This limit complicates the design of the circuit. In addition, the series connection of ESD protection circuits will increase costs.
Referring to the structure configuration of FIG. 2, the control gate of the PSCR 141a is coupled to the first power source Vdd1, and the control gate of the PSCR 143a is coupled to the second power source Vdd2. As a result, N-well regions of these PSCRs 141a and 143a must be separated, and cannot be a same N-well. The structure of NSCRs 141b and 143b has the same issue. This would increase the layout area of the circuit and increase costs.